1. Field of the Invention
Embodiments of the present invention relate to the field of automated multisite testing. More particularly, embodiments of the present invention relate generally to reconverging test flow execution sub-paths in a test sequence. Other embodiments of the present invention relate generally to the assignment of priority values for testing operations in a test flow.
2. Related Art
Automatic Test Equipment (ATE) is used in the manufacture of semiconductor integrated circuits (IC chips), or dice on a wafer, to test the dice electrically to characterize the fabrication process, define operating parameters, and to ensure that they are free of manufacturing defects. Manufacturing costs of the dice are tied to the capital cost for the ATE as well as the operating cost of the ATE during testing of the dice. In particular, as the testing sequence executed by the ATE becomes longer, the operating cost of the ATE can be a significant portion of the cost of a single die. As such, reducing the operating cost of the ATE is of paramount importance.
Multisite testing is one approach to lessen the operating cost of ATE when testing integrated circuits. Testing efficiency is gained when multiple sites on an ATE perform the same operation simultaneously. In general, efficiency is gained when multiple sites on an ATE share the same testing resources on the ATE. On the other hand, efficiency is decreased when the devices at different sites on the ATE behave differently during test, forcing different sites to follow different execution paths through a test flow.
However, multisite testing in the prior art typically has been reduced to a single execution flow once devices at different sites on the ATE diverge during testing. In a single execution flow, multiple dice performing similarly are tested by executing numerous testing operations in a particular execution path. In multisite testing of the prior art, as long as the dice all perform similarly, then the efficiency is maintained, since the ATE can perform testing operations simultaneously on the dice. However, once dice behave differently, testing continues serially for the various groups of dice that behave differently.
In particular, for many IC chip designs, the flow associated with testing may have branching testing sequences. As such, the flow is comprised of numerous execution paths that a die may follow during test. Depending on which execution path is followed, various results may be attributed to the die. This is common in the case of “speed binning,” for example, when an IC chip that operates at a high frequency can be separated out during testing and sold for a premium. Similarly, IC chips that fail at the higher frequency may be retested at a lower frequency through a separate execution path.
During multisite testing, it is usually not possible for the ATE to simultaneously test two different dice at different frequencies. In the prior art, dice that fail at the higher frequency are disabled during testing after a branch point, and testing continues for those dice that pass. Once testing terminates on the dice at the higher frequency, then the disabled dice that originally failed at the higher frequency are re-enabled, and testing continues at the lower frequency. In effect, the multisite testing of the prior art has been reduced to multiple single execution paths for the various dice that perform differently. In that case, the efficiencies of multisite testing are diminished since there is less simultaneous sharing of the ATE resources.